You are kindly invited to:
Hardware & Software Co-Design & Co-Verification
Tuesday, September 8, 2009, 8:00 - 17:00
Auditorium Floor 2, Room 280, Electrical Engineering Building, Technion

Please Register Online!

Schedule

08:00 - 08:20

Reception and Light Refreshments

08:20 - 08:30

Opening

08:30 - 09:20

Hardware from Mars, Software from Venus: A Marriage made in heaven?
Keynote Speaker
Yishai Fraenkel, Intel


09:20 - 10:10

Verification And Debugging Of Hardware, Designs Utilizing C-Based High-Level Design Descriptions
Masahiro Fujita, Tokyo University


10:10 - 10:30

Coffee Break

10:30 - 11:20

Architecture-Aware Analysis Of Concurrent Software
Rajeev Alur, University of Pennsylvania


11:20 - 12:10

Towards Rigorous Relaxed Memory Models
Peter Sewell, Cambridge University


12:15 - 14:00

Lunch

14:00 - 14:50

Game Semantics And Compositional Equivalence Checking Of Imperative Programs
Luke Ong, Oxford University


14:50 - 15:40

Regression Verification: Proving The Equivalence Of Similar Programs
Ofer Strichman, Technion


15:40 - 16:00

Coffee Break

16:00 - 16:50

Model Checking Using Message Sequence Charts
Doron Peled, Bar Ilan Univsity


16:50 - 17:00

Closing

For more information please call Sharon Raz 04-8656525

sharon.raz@intel.com

 

Full Program: http://workshop.ee.technion.ac.il/dts09

Registration Form

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