Please, Register Online!

 

 

 

 

 

 

              

The Workshop is in English!            

You are kindly invited to:
Test and Debug
Monday, September 13, 2010, 8:00 - 16:00
Auditorium Floor 2, Room 280, Electrical Engineering Building, Technion
Schedule

08:00 - 08:20

Reception and Light Refreshments

08:20 - 08:40

Opening

08:40 - 09:20

Challenges in Test & Debug of the New Generation HVM Microprocessors
Arik Shemer (Stramer) (Intel Haifa) Keynote


09:20 - 10:10

Self-Testing and Self-Tuning Mixed-Signal/RF Systems
Abhijit Chatterjee (Georgia Tech)


10:10 - 10:30

Coffee Break

10:30 - 11:20

Coverage Metrics for Post-Silicon Validation
K.-T. Tim Cheng (Univ. of California, Santa Barbara)


11:20 - 12:10

Post-Silicon Validation of Robust Systems
Subhasish Mitra (Stanford Univ.)


12:15 - 14:00

Lunch

14:00 - 14:50

Thermal Modeling, Management and Optimiza¬tion for High-Performance IC Testing
Niraj Jha (Princeton Univ.):


14:50 - 15:40

Combining Pre-Silicon Verification Brains with Post-Silicon Platform Muscle
Amir Nahir (IBM Haifa)


15:40 - 16:00

Closing

For more information please call Sharon Raz 04-8656525

 sharon.raz@intel.com

 

http://workshop.ee.technion.ac.il/dts10

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