Please Register Online

        

 

 

 

                                             

 

                          The Symposium is in English

You are kindly invited to:
Intel & Technion Symposium 2011
Tuesday, September 13, 2011, 8:20 - 17:40
Auditorium Floor 2, Room 280, Electrical Engineering Building, Technion

Challenges and Opportunities in System-level Design & Verification

Schedule

08:20 - 08:30

Opening

08:30 - 09:10

Challenges and Opportunities in System-level Design and Verification
Keynote: Yehuda Adelman,Intel


09:10 - 10:00

Software-Defined Everything: High-Level Design and Validation
Grant Martin, Tensilica


10:00 - 10:20

Break

10:20 - 11:35

On Behavioral Programming
David Harel, Weizmann Institute


11:35 - 12:25

Taking Formal into Areas Unaccustomed to It
Ganesh Gopalakrishnan, Utah University


12:25 - 14:00

Lunch

14:00 - 14:50

Towards High-Level Models For Low-Power Systems
Florence Maraninchi, Verimag


14:50 - 15:40

Inherent limitations facilitate design and verification of concurrent programs
Hagit Attiya, Technion


15:40 - 16:00

Break

16:00 - 16:50

Trustworthy Hardware from Certified Behavioral Synthesis
Fei Xie, Portland State University


16:50 - 17:40

Transaction Based Sequential Equivalence Checking of High Level Designs against RTL: Tips, Tricks, and Challenges
Pankaj Chauhan, Calypto Design Systems


 

For more information please call Littal Dori 04-8651884

littal.dori@intel.com

 

Organized by 

Khasidashvili Zurab &Korchemny Dmitry - Intel

Prof. Tsahi Birk - Technion

 

Registration Form

 

Technion MAP